Improving Packet Processing Efficiency on Multi-core Architectures with Single Input Queue

Generic purpose multi-core PC architectures are facing performance challenges of high rate packet reception on gigabit per second and higher speed network interfaces. In order to assign a CPU core to a networking softIRQ, the single input queue design of the low-level packet processing subsystem relies on the kernel's Symmetric Multiprocessing (SMP) scheduler, which does not perform load balancing of the softIRQ instances between the CPU cores. In practice, when single receive queue is used all of the softIRQs are assigned to a single CPU core. This typical arrangement could easily drive to CPU resource exhaustion and high packet loss ratio on high bandwidth interfaces. The non-steady state of the system is triggered by the high arrival rate of the packets. This work presents a proposal for improving the packet processing efficiency in single input queue multi-core systems.